1. Field of the Invention
The present invention relates to a power amplifier circuit which amplifies a radiofrequency signal and, more particularly, to a power amplifier circuit capable of increasing power efficiency both during high-power operation and during low-power operation.
2. Background Art
A power amplifier circuit is designed so as to maximize the power efficiency at the time of amplification of power to a high level in order to improve the power efficiency. This means that the power efficiency is reduced at the time of amplification to a level lower than the high level.
FIG. 12 is a block diagram showing an example of a conventional power amplifier circuit, which is provided with amplifying transistors 22 and 24 in two stages. A power supply voltage (3.5 V) is applied to terminals Vc1, Vc2, and Vcb. When an ON signal is supplied to a control terminal cont1, the control circuit 14 operates the amplifying transistors 22 and 24. A radiofrequency signal supplied to an input terminal IN passes an input matching circuit 21, the amplifying transistor 22 in the first stage, an interstage matching circuit 23, the amplifying transistor 24 in the second stage and an output matching circuit 25 one after another and is output from an output terminal OUT.
FIG. 13 is a diagram showing the relationship between the output power and the power efficiency of a conventional power amplifier circuit. For example, a transmission power amplifier circuit for use in CDMA (code division multiple access) telephones has a maximum output of 27 dBm and the power efficiency when the power amplifier circuit outputs this power (in high-power operation) is about 45%. On the other hand, the power efficiency at an output of 17 dBm (in low-power operation) is extremely low, about 15%. Therefore the power supply voltage in low-power operation is reduced to improve the efficiency. For example, the power efficiency is improved to about 25% by reducing the power supply voltage to 1.5 V. However, there is a problem that a need arises for a DC/DC converter for reducing the power supply voltage.
FIG. 14 is a block diagram showing another example of the conventional power amplifier circuit. This amplifier circuit has a bypass circuit 61 for bypassing the amplifying transistor 24 in the second stage. When an OFF signal is supplied to a control terminal cont2, the control circuit 14 stops the operation of the amplifying transistor 24 in the second stage. The signal is then output via the bypass circuit 61. In this case, no current flows through the amplifying transistor 24 in the second stage, so that the power efficiency is increased. Even when the ordinary power supply voltage is fixed at 3.5 V, a power efficiency of about 25% can be obtained, for example, at an output of 16 dBm (in low-power operation).
In this arrangement, there is a need for a selection switch or a combining circuit for combining signals from the two paths in the output section. FIG. 15 is a diagram showing a conventional power amplifier circuit using a selection switch 62. FIG. 16 is a diagram showing a conventional power amplifier circuit using a combining circuit 13 (see, for example, Japanese Patent Laid-Open No. 2001-185967).
Power efficiency η is expressed by η=output power/power supply voltage/consumption current. If no combining circuit or the like is provided, and if the output power is 27 dBm; the power supply voltage is 3.5 V; and the power efficiency is 45%, the consumption current is Ict 1027/10/3.5/0.45=318 mA.
On the other hand, if the loss in a combining circuit or the like is 0.5 dB, power of 27.5 dBm is required in the stage before the combining circuit or the like. Accordingly, if the power efficiency at the stage before the combining circuit or the like is 45%, the consumption current is Ict 1027.5/10/3.5/0.45=357 mA. Accordingly, the output from the power amplifier circuit decreases by 0.5 dB to be 27 dBm, and the power efficiency at the stage following the combining circuit or the like is reduced to 40%. That is, the circuits shown in FIGS. 14 to 16 are capable of improving the power efficiency during low-power operation but have reduced power efficiency during high-power operation.